Fujitsu Limited and Denali Software, Inc. today announced their co-development of a DDR DRAM physical interface (DDR PHY)(1)product compatible with the recently announced DDR-PHY Interface (DFI) version 1.0 specification.
The DDR PHY utilizes the DFI specification which defines a common interface between the conventional proprietary memory controller logic and DDR PHY designs, which reduces design and integration costs for developing DDR DRAM memory systems, and reduces overall time-to-market.
"DDR DRAM memory system design has emerged as a significant design challenge that affects a wide range of applications, spanning communications, computing, networking, and consumer electronics such as digital audio-videos," said Brian Gardner, vice president of IP products at Denali Software.
"A key part of the solution involves decoupling the DDR PHY design, which is highly process dependent and timing sensitive, from the DDR controller logic design, which is driven by system performance requirements.
The DFI specification provides a clean boundary between these two memory system components, and enables developers to use best-in-class PHY and memory controller designs.
Fujitsu's new DFI compatible DDR PHY designs are a demonstration of state-of-the-art solutions for ASIC development, and provide customers with a significant advantage in DDR memory system development."
About the DDR PHY Interface (DFI) Specification
The DFI specification was developed by expert contributors from recognized leaders in the semiconductor, IP, and electronic design automation (EDA) industries.
The DFI specification defines an interface protocol between memory controller logic and PHY interfaces, with the goal of reducing costs for integrating DDR memory controller logic and DDR PHY interface while increasing performance and data throughput efficiency. The protocol defines the signals, timing, and functionality required for efficient communication across the interface.
This enables reducing design and verification cost and time-to-market while increasing the potential for reusing the individual components that compose the memory system. The DFI Specification version 1.0 was released for production development in January 2007.
Time of Release
The DFI compatible DDR1 IF PHY up to 400 Mbps and the DFI compatible DDR2 IF PHY beyond 400 Mbps will be released at the end of September, 2007, and the end of November, 2007 for ASIC and COT using Fujitsu's 90 nm or further advanced process technologies, respectively
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