December 2007
Tokyo,— Fujitsu Laboratories Ltd. and Fujitsu Limited announced their development of technology that enables high-reliability multi-layer interconnects for logic LSIs for 32nm generation and beyond, by using copper with manganese additives in combination with an ultra-thin film barrier metal.
Compared to conventional technology, Fujitsu's new technology effectively reduces line resistance in interconnects, and increases endurance against electro-migration- a cause of LSI degradation over time. This technology will enable Fujitsu to provide highly-integrated high-performance LSIs to customers.
In accordance with electronic devices becoming further compact, as microprocessors becoming increasingly higher in performance and mobile information devices become more multi-functional, there is a growing demand for high-performance, logic LSI devices that feature higher levels of integration and consume less power, a trend that is also driving the development of finer interconnects used in LSI devices.
For example, the 32nm generation of logic LSIs that are currently under development will be using copper interconnects measuring 50nm wide. In order to enable the development of higher-performance LSIs, technology capable of achieving high reliability becomes necessary, by limiting the rise of interconnect resistance while in addition reducing age degradation of interconnects.
Up through the 45nm generation of LSIs, copper interconnects were wrapped in a barrier metal for protection. The barrier metal is necessary to prevent the diffusion of copper into the insulating film, and to prevent the insulating film from oxidizing the copper.
A thick barrier metal improves reliability, but at the 32nm generation level of miniaturization, the barrier metal would occupy a disproportionate amount of space relative to the copper interconnect, thereby increasing the line resistance of the interconnect.
Thus, the need to reduce line resistance while maintaining reliability has become a pressing issue.
Compared to the copper interconnect barrier metal combination method that had been used up to the 45nm generation, this new technique from Fujitsu for multi-layer interconnects enables the reduction of thickness of barrier-metal films by one-third, and effectively reduces interconnect line resistance to levels that meet the standards laid out for the 32nm generation in the International Technology Roadmap for Semiconductors (ITRS).
In addition, by increasing endurance lifetime against electro-migration – a cause for degradation over time - by a factor of 47, high reliability applicable for highly integrated minute interconnects for the 32nm generation and beyond is achieved.
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