December 2007
Tokyo, December 13, 2007 - NEC Corporation and NEC Electronics Corporation have successfully developed design technology to realize optimum channel structure in CMOS transistors for advanced LSIs in the 32nm generation and beyond.
This achievement relies on visualization of impurity distributions in transistors based on electron beam holography technology with world-leading high spatial resolution.
Features of the new technology:
The functionality of electronic equipment, such as mobile phones, digital consumer electronics, mobile audio players, and car navigation systems, is becoming increasingly diverse with advances in IT network accessibility.
This has generated strong demand for improvements in performance, power consumption and manufacturing costs of modern LSI devices, which in turn drives expectation for the realization of technologies to further miniaturize LSIs.
The major technical challenge with modern advanced CMOS devices is how to suppress the trend of increasing leakage current, which arises from the miniaturization of device structures.
To overcome this problem, it is necessary to form ultra-shallow junctions in the channel regions of transistors; however, ultra-shallow junctions may potentially cause degradation in device performance due to increased parasitic resistance.
Therefore, it is necessary to carefully optimize the junction structures (profiles) to meet the requirements for both performance enhancement and suppressed leakage current.
To achieve these requirements, optimum shapes for the ultra-shallow junctions based on TCAD (process simulations), whose results yield optimum process conditions to realize ideal junction structures, need to be designed.
As the actual junction structure is known to be very sensitive to the parameters for fabrication processes, there is a demand for a highly accurate nanometer-scale metrology technique that allows tuning of the process parameters through observation of junction structures built in the actual devices.
From the point of view of process technology, an ion-implantation technique capable of introducing impurity atoms only into the very shallow region from the surface of silicon crystals is required.
Furthermore, an annealing technique with a minimal thermal budget is needed to achieve electrical activation of impurities without inducing their notable redistribution through thermal diffusion.
NEC and NEC Electronics' research achievement meets these expectations and realizes shape control of the ultra-shallow junctions, as well as optimization of the fabrication processes.
The research result demonstrated that planar-bulk-type CMOS devices can be miniaturized down to the 30nm generation, while maintaining good performance and suppressed leakage current.
NEC and NEC Electronics will continue this research toward delivery of system LSIs with improved performance and quality, indispensable to the realization of a ubiquitous-networked society.
This research was presented on December 10 at the International Electron Device Meeting (IEDM) being held in Washington DC.
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