January 2008
Lattice Semiconductor Corporation announced the immediate availability of Service Pack 2 for Version 7.0 of its ispLEVER® FPGA design tool suite. The release adds additional usability and accuracy enhancements to the Power Calculator, new versions of Synplicity’s Synplify synthesis and Mentor Graphics’ Precision RTL synthesis, and new support for the LatticeMico32™ embedded open source microprocessor.
This latest release of the LatticeMico32 adds support for multiple bus arbitration schemes, allows VHDL users to implement the LatticeMico32 in their designs and adds Linux OS-based development tools. The Mico System Builder automatically generates the appropriate Wishbone Bus arbitration scheme when the microprocessor platform is generated for shared-bus or slave-side arbitration to allow multiple master ports access to multiple slave ports.
“Each release of ispLEVER delivers material improvements with immediate benefits to our users,” said Tim Schnettler, director of design tools marketing at Lattice. “The ispLEVER Power Calculator continues to provide the accurate estimates that users need to impact their design cycle early in the process and Linux Operating System support for the development tools expands the potential user base for our LatticeMico32 embedded microprocessor.”
Chris Fanning, corporate vice president, enterprise solutions, said, “Lattice continues to introduce performance and functional improvements to its ispLEVER design tool that enhance FPGA designers’ productivity, and their ability to rapidly and effectively complete their designs. Customers continue to use our open source LatticeMico32 at an accelerating rate and our latest enhancements are the direct result of this significant customer feedback.”
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