March 2008
Seiko Epson Corporation ("Epson") announced that it has developed the S7R77024, a new 3-channel, 16-bit analog front end (AFE) capable of speeds of up to 75 mega-samples per second, and higher copying speeds for MFPs (multi-functional peripherals) in the SOHO (small office home office) environment. Volume production of this new product is expected to commence at the end of March 2008, with a projected output of more than 50,000 units per month.
The S7R77024 incorporates a high-performance timing generator capable of controlling various types of CCD (charge-coupled device) and CIS (conductor image sensor), and an LVDS (low-voltage differential signalling) output function for image data output. Furthermore, Epson's own built-in automatic offset and gain adjustment function enables ideal values to be easily set for input to each of the three channels independently.
Although the S7R77024 is a 3-channel product, it can be used with one or two channels, making it suited to a wide variety of equipment, ranging from monochrome copying machines to color copying machines. For these applications, the sampling rate (A/D converter rate) is 25 Msps for one channel; 50 Msps for two channels; and 75 MSPS for three channels. Moreover, as the image data format of the LVDS output can be changed as needed, the S7R77024 facilitates the development of systems by making possible the use of various elements such as enabling connection with existing SoC.
Incorporating these functions in the S7R77024 not only enables the MFP to achieve high reading speeds in excess of 40 sheets per minute for color, but also reduces EMI, and makes it possible to provide a platform applicable to monochrome copying machines as well as color copying machines, thereby significantly contributing to the development of systems.
In conjunction with the release of the S7R77024, Epson will provide the S1R77084 LVDS Channel Link Receiver as a companion chip to the product. The S1R77084 is a QFP-48-pin package that converts three LVDS data streams back into 21-bit CMOS/TTL data to enable interfacing with SoC. Using the S1R77084 together with the S7R77024 will substantially reduce EMI and the number of cables needed in the data transfer unit, and also improve the reliability of data transfer.
In order to continue to meet the various demands of its customers, Epson will expand its lineup of devices that utilize its core technologies of Low Power Analog IP, Low Current Leakage Process, and Eco-friendly Power Algorithm.
Features of the new product:
1. High-performance timing generator
* Generates the shift signals necessary to control various CCD; capable of inversion control by setting registers
* Generates drive clock signals required for driving CCD and AFE; sets ADCK by dividing one cycle
* Capable of setting delay of drive clock signal in increments as small as 1.3ns
* Capable of freely setting drive clock pattern and shift signal output timing
* Capable of generating black reference pixels (optical shield) and effective pixel output timing to facilitate synchronicity with SoC
* Generates necessary signals within CCD board through built-in oscillation circuit, contributing to reduction in number of communication signal lines and reduction of EMI
2. AFE specifications that are top-class in the industry
* Transfer speed of up to 75 Msps for color images
* Automatic offset/gain adjustment
* Programmable gain amplifier adjustment: 8-bit
* Offset adjustment: 10-bit
3. LVDS image data output
* 7 bits/cycle Channel Link output
* Capable of outputting image data and control signals
* Capable of freely setting the format of the bits output, the number of bits output, and various control signals through the registers
* Capable of utilizing from one stream to three streams depending on the transfer speed
* Form Chipset with S1R77084 Channel Link Receiver
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